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| d a t a sh eet product speci?cation supersedes data of 1998 feb 06 file under integrated circuits, ic12 2001 oct 02 integrated circuits pcf8576 universal lcd driver for low multiplex rates
2001 oct 02 2 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 contents 1 features 2 general description 3 ordering information 4 block diagram 5 pinning 6 functional description 6.1 power-on reset 6.2 lcd bias generator 6.3 lcd voltage selector 6.4 lcd drive mode waveforms 6.5 oscillator 6.5.1 internal clock 6.5.2 external clock 6.6 timing 6.7 display latch 6.8 shift register 6.9 segment outputs 6.10 backplane outputs 6.11 display ram 6.12 data pointer 6.13 subaddress counter 6.14 output bank selector 6.15 input bank selector 6.16 blinker 7 characteristics of the i 2 c-bus 7.1 bit transfer (see fig.12) 7.2 start and stop conditions (see fig.13) 7.3 system configuration (see fig.14) 7.4 acknowledge (see fig.15) 7.5 pcf8576 i 2 c-bus controller 7.6 input filters 7.7 i 2 c-bus protocol 7.8 command decoder 7.9 display controller 7.10 cascaded operation 8 limiting values 9 handling 10 dc characteristics 11 ac characteristics 11.1 typical supply current characteristics 11.2 typical characteristics of lcd outputs 12 application information 12.1 chip-on-glass cascadability in single plane 13 bonding pad information 14 tray information: PCF8576U 15 tray information: PCF8576U/2 16 package outlines 17 soldering 17.1 introduction to soldering surface mount packages 17.2 reflow soldering 17.3 wave soldering 17.4 manual soldering 17.5 suitability of surface mount ic packages for wave and reflow soldering methods 18 data sheet status 19 definitions 20 disclaimers 21 purchase of philips i 2 c components 2001 oct 02 3 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 1 features single-chip lcd controller/driver selectable backplane drive configuration: static or 2/3/4 backplane multiplexing selectable display bias configuration: static, 1 2 or 1 3 internal lcd bias generation with voltage-follower buffers 40 segment drives: up to twenty 8-segment numeric characters; up to ten 15-segment alphanumeric characters; or any graphics of up to 160 elements 40 4-bit ram for display data storage auto-incremented display data loading across device subaddress boundaries display memory bank switching in static and duplex drive modes versatile blinking modes lcd and logic supplies may be separated wide power supply range: from 2 v for low-threshold lcds and up to 9 v for guest-host lcds and high-threshold (automobile) twisted nematic lcds low power consumption power-saving mode for extremely low power consumption in battery-operated and telephone applications i 2 c-bus interface ttl/cmos compatible compatible with any 4-bit, 8-bit or 16-bit microprocessors/microcontrollers may be cascaded for large lcd applications (up to 2560 segments possible) cascadable with 24-segment lcd driver pcf8566 optimized pinning for plane wiring in both single and multiple pcf8576 applications space-saving 56-lead plastic very small outline package (vso56) very low external component count (at most one resistor, even in multiple device applications) compatible with chip-on-glass technology manufactured in silicon gate cmos process. 2 general description the pcf8576 is a peripheral device which interfaces to almost any liquid crystal display (lcd) with low multiplex rates. it generates the drive signals for any static or multiplexed lcd containing up to four backplanes and up to 40 segments and can easily be cascaded for larger lcd applications. the pcf8576 is compatible with most microprocessors/microcontrollers and communicates via a two-line bidirectional i 2 c-bus. communication overheads are minimized by a display ram with auto-incremented addressing, by hardware subaddressing and by display memory switching (static and duplex drive modes). 3 ordering information type number package name description version pcf8576t vso56 plastic very small outline package; 56 leads sot190-1 PCF8576U - chip in tray - PCF8576U/2 - chip with bumps in tray - PCF8576U/5 - unsawn wafer - PCF8576U/10 ffc chip on ?lm frame carrier (ffc) - PCF8576U/12 ffc chip with bumps on ?lm frame carrier (ffc) - 2001 oct 02 4 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 4 block diagram handbook, full pagewidth mbk276 lcd voltage selector v lcd 12 v dd 5 r r r timing blinker oscillator input filters i c - bus controller 2 power- on reset clk 4 sync 3 osc 6 v ss 11 scl 2 sda 1 sa0 10 display controller command decoder backplane outputs 13 bp0 14 bp2 15 bp1 16 bp3 input bank selector display ram 40 x 4 bits output bank selector data pointer sub- address counter display segment outputs display latch shift register 17 to 56 s0 to s39 a0 7 a1 8 a2 9 pcf8576 lcd bias generator 40 fig.1 block diagram (for vso56 package; sot190-1). 2001 oct 02 5 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 5 pinning symbol pin description sda 1 i 2 c-bus serial data input/output scl 2 i 2 c-bus serial clock input sync 3 cascade synchronization input/output clk 4 external clock input/output v dd 5 supply voltage osc 6 oscillator input a0 to a2 7 to 9 i 2 c-bus subaddress inputs sa0 10 i 2 c-bus slave address input; bit 0 v ss 11 logic ground v lcd 12 lcd supply voltage bp0, bp2, bp1 and bp3 13 to 16 lcd backplane outputs s0 to s39 17 to 56 lcd segment outputs 2001 oct 02 6 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 fig.2 pin configuration; sot190-1. handbook, halfpage pcf8576t mbk278 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 sda scl sync clk v osc a0 a1 a2 sa0 v v bp0 bp2 bp1 bp3 s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 s39 s38 s37 s36 s35 s34 s33 s32 s31 s30 s29 s28 s27 s26 s25 s24 s23 s22 s21 s20 s19 s18 s17 s16 s15 s14 s13 s12 dd ss lcd 2001 oct 02 7 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 6 functional description the pcf8576 is a versatile peripheral device designed to interface to any microprocessor/microcontroller to a wide variety of lcds. it can directly drive any static or multiplexed lcd containing up to four backplanes and up to 40 segments. the display configurations possible with the pcf8576 depend on the number of active backplane outputs required; a selection of display configurations is given in table . all of the display configurations given in table can be implemented in the typical system shown in fig.3. the host microprocessor/microcontroller maintains the 2-line i 2 c-bus communication channel with the pcf8576. the internal oscillator is selected by connecting pin osc to pin v ss . the appropriate biasing voltages for the multiplexed lcd waveforms are generated internally. the only other connections required to complete the system are to the power supplies (v dd , v ss and v lcd ) and the lcd panel chosen for the application. selection of display con?gurations number of 7-segments numeric 14-segments alphanumeric dot matrix backplanes segments digits indicator symbols characters indicator symbols 4 160 20 20 10 20 160 dots (4 40) 3 120 15 15 8 8 120 dots (3 40) 2 80 10 10 5 10 80 dots (2 40) 1 40552 1240 dots (1 40) fig.3 typical system configuration. handbook, full pagewidth host micro- processor/ micro- controller r t r 2c b sda scl osc r osc 1 17 to 56 13 to 16 2 6 78 512 91011 40 segment drives 4 backplanes lcd panel (up to 160 elements) pcf8576 a0 a1 a2 ss sa0 v ss v dd v dd v lcd v mbk277 2001 oct 02 8 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 6.1 power-on reset at power-on the pcf8576 resets to a starting condition as follows: 1. all backplane outputs are set to v dd . 2. all segment outputs are set to v dd . 3. the drive mode 1 : 4 multiplex with 1 3 bias is selected. 4. blinking is switched off. 5. input and output bank selectors are reset (as defined in table 4). 6. the i 2 c-bus interface is initialized. 7. the data pointer and the subaddress counter are cleared. data transfers on the i 2 c-bus should be avoided for 1 ms following power-on to allow completion of the reset action. 6.2 lcd bias generator the full-scale lcd voltage (v op ) is obtained from v dd - v lcd . the lcd voltage may be temperature compensated externally through the v lcd supply to pin 12. fractional lcd biasing voltages are obtained from an internal voltage divider of the three series resistors connected between v dd and v lcd . the centre resistor can be switched out of the circuit to provide a 1 2 bias voltage level for the 1 : 2 multiplex configuration. 6.3 lcd voltage selector the lcd voltage selector co-ordinates the multiplexing of the lcd in accordance with the selected lcd drive configuration. the operation of the voltage selector is controlled by mode set commands from the command decoder. the biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of v op =v dd - v lcd and the resulting discrimination ratios (d), are given in table 1. a practical value for v op is determined by equating v off(rms) with a defined lcd threshold voltage (v th ), typically when the lcd exhibits approximately 10% contrast. in the static drive mode a suitable choice is v op >3v th approximately. multiplex drive ratios of 1 : 3 and 1 : 4 with 1 2 bias are possible but the discrimination and hence the contrast ratios are smaller ( = 1.732 for 1 : 3 multiplex or = 1.528 for 1 : 4 multiplex). the advantage of these modes is a reduction of the lcd full-scale voltage v op as follows: 1 : 3 multiplex ( 1 2 bias): v op = = 2.449 v off(rms) 1 : 4 multiplex ( 1 2 bias): v op = = 2.309 v off(rms) these compare with v op =3v off(rms) when 1 3 bias is used. 3 21 3 ---------- 6v off rms ? 43 () 3 --------------------- - table 1 preferred lcd drive modes: summary of characteristics lcd drive mode number of lcd bias configuration backplanes levels static 1 2 static 0 1 1:2 2 3 1 2 0.354 0.791 2.236 1:2 2 4 1 3 0.333 0.745 2.236 1:3 3 4 1 3 0.333 0.638 1.915 1:4 4 4 1 3 0.333 0.577 1.732 v off(rms) v op -------------------- - v on(rms) v op -------------------- - d v on(rms) v off(rms) -------------------- - = 2001 oct 02 9 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 6.4 lcd drive mode waveforms the static lcd drive mode is used when a single backplane is provided in the lcd. backplane and segment drive waveforms for this mode are shown in fig.4. when two backplanes are provided in the lcd, the 1 : 2 multiplex mode applies. the pcf8576 allows use of 1 2 bias or 1 3 bias in this mode as shown in figs 5 and 6. when three backplanes are provided in the lcd, the 1 : 3 multiplex drive mode applies, as shown in fig.7. when four backplanes are provided in the lcd, the 1 : 4 multiplex drive mode applies, as shown in fig.8. v state1 t () v s n t () v bp0 t () C = v on(rms) v op = v state2 t () v s n1 + t () v bp0 t () C = v off(rms) 0v = fig.4 static drive mode waveforms (v op =v dd - v lcd ). mbe539 v dd v lcd v lcd v dd v lcd v op v op state 1 0 bp0 s n s n 1 v op v op state 2 0 (a) waveforms at driver (b) resultant waveforms at lcd segment lcd segments state 1 (on) state 2 (off) t frame v dd 2001 oct 02 10 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 fig.5 waveforms for the 1 : 2 multiplex drive mode with 1 2 bias (v op =v dd - v lcd ). v state1 t () v s n t () v bp0 t () C = v on(rms) 0.791v op = v state2 t () v s n t () v bp1 t () C = v off(rms) 0.354v op = mbe540 v (v )/2 v dd v /2 op v op state 1 0 bp0 s n 1 (a) waveforms at driver (b) resultant waveforms at lcd segment lcd segments state 2 t frame dd lcd v lcd bp1 s n v op v /2 op v /2 op v op state 2 0 v op v /2 op state 1 v (v )/2 v dd dd lcd v lcd v lcd v lcd v dd v dd 2001 oct 02 11 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 fig.6 waveforms for the 1 : 2 multiplex drive mode with 1 3 bias (v op =v dd - v lcd ). v state1 t () v s n t () v bp0 t () C = v on(rms) 0.745v op = v state2 t () v s n t () v bp1 t () C = v off(rms) 0.333v op = mbe541 v dd 2v /3 op v op state 1 0 bp0 s n 1 (a) waveforms at driver (b) resultant waveforms at lcd segment lcd segments state 2 t frame v v /3 dd op v lcd bp1 s n v op state 1 v 2v /3 dd op v dd v v /3 dd op v lcd v 2v /3 dd op v dd v v /3 dd op v lcd v 2v /3 dd op v dd v v /3 dd op v lcd v 2v /3 dd op v /3 op 2v /3 op v /3 op 2v /3 op v op state 2 0 v op v /3 op 2v /3 op v /3 op 2001 oct 02 12 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 mbe542 2v /3 op v op state 1 0 bp0 (b) resultant waveforms at lcd segment lcd segments state 2 t frame bp1 v op state 1 v /3 op 2v /3 op v /3 op 2v /3 op v op state 2 0 v op v /3 op 2v /3 op v /3 op s n 1 s n 2 (a) waveforms at driver s n bp2/s23 v dd v v /3 dd op v lcd v 2v /3 dd op v dd v v /3 dd op v lcd v 2v /3 dd op v dd v v /3 dd op v lcd v 2v /3 dd op v dd v v /3 dd op v lcd v 2v /3 dd op v dd v v /3 dd op v lcd v 2v /3 dd op v dd v v /3 dd op v lcd v 2v /3 dd op fig.7 waveforms for the 1 : 3 multiplex drive mode (v op =v dd - v lcd ). v state1 t () v s n t () v bp0 t () C = v on(rms) 0.638v op = v state2 t () v s n t () v bp1 t () C = v off(rms) 0.333v op = 2001 oct 02 13 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 fig.8 waveforms for the 1 : 4 multiplex drive mode (v op =v dd - v lcd ). mbe543 2v /3 op v op state 1 0 bp0 (b) resultant waveforms at lcd segment lcd segments state 2 t frame bp1 v op state 1 v /3 op 2v /3 op v /3 op 2v /3 op v op state 2 0 v op v /3 op 2v /3 op v /3 op s n 1 bp2 s n 2 s n 3 (a) waveforms at driver s n bp3 v dd v v /3 dd op v lcd v 2v /3 dd op v dd v v /3 dd op v lcd v 2v /3 dd op v dd v v /3 dd op v lcd v 2v /3 dd op v dd v v /3 dd op v lcd v 2v /3 dd op v dd v v /3 dd op v lcd v 2v /3 dd op v dd v v /3 dd op v lcd v 2v /3 dd op v dd v v /3 dd op v lcd v 2v /3 dd op v dd v v /3 dd op v lcd v 2v /3 dd op v state1 t () v s n t () v bp0 t () C = v on(rms) 0.577v op = v state2 t () v s n t () v bp1 t () C = v off(rms) 0.333v op = 2001 oct 02 14 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 6.5 oscillator 6.5.1 i nternal clock the internal logic and the lcd drive signals of the pcf8576 are timed either by the internal oscillator or from an external clock. when the internal oscillator is used, pin osc should be connected to pin v ss . in this event, the output from pin clk provides the clock signal for cascaded pcf8566s in the system. where resistor r osc to v ss is present, the internal oscillator is selected. the relationship between the oscillator frequency on pin clk (f clk ) and r osc is shown in fig.9. 6.5.2 e xternal clock the condition for external clock is made by connecting pin osc to pin v dd ; pin clk then becomes the external clock input. the clock frequency (f clk ) determines the lcd frame frequency and the maximum rate for data reception from the i 2 c-bus. to allow i 2 c-bus transmissions at their maximum data rate of 100 khz, f clk should be chosen to be above 125 khz. a clock signal must always be supplied to the device; removing the clock may freeze the lcd in a dc state. 6.6 timing the timing of the pcf8576 organizes the internal data flow of the device. this includes the transfer of display data from the display ram to the display segment outputs. in cascaded applications, the synchronization signal sync maintains the correct timing relationship between the pcf8576s in the system. the timing also generates the lcd frame frequency which it derives as an integer multiple of the clock frequency (see table 2). the frame frequency is set by the mode set commands when internal clock is used, or by the frequency applied to pin clk when external clock is used. the ratio between the clock frequency and the lcd frame frequency depends on the mode in which the device is operating. in the power-saving mode the reduction ratio is six times smaller; this allows the clock frequency to be reduced by a factor of six. the reduced clock frequency results in a significant reduction in power dissipation. the lower clock frequency has the disadvantage of increasing the response time when large amounts of display data are transmitted on the i 2 c-bus. when a device is unable to digest a display data byte before the next one arrives, it holds the scl line low until the first display data byte is stored. this slows down the transmission rate of the i 2 c-bus but no data loss occurs. table 2 lcd frame frequencies 6.7 display latch the display latch holds the display data while the corresponding multiplex signals are generated. there is a one-to-one relationship between the data in the display latch, the lcd segment outputs and one column of the display ram. 6.8 shift register the shift register serves to transfer display information from the display ram to the display latch while previous data is displayed. fig.9 oscillator frequency as a function of r osc . f clk 3.4 10 7 r osc ----------------------- - ? ? ?? khz () ? 10 4 mbe531 10 3 10 2 10 10 3 10 2 f clk (khz) r(k w) osc min max pcf8576 mode frame frequency nominal frame frequency (hz) normal mode 64 power-saving mode 64 f clk 2880 ------------ - f clk 480 --------- - 2001 oct 02 15 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 6.9 segment outputs the lcd drive section includes 40 segment outputs pins s0 to s39 which should be connected directly to the lcd. the segment output signals are generated in accordance with the multiplexed backplane signals and with data resident in the display latch. when less than 40 segment outputs are required the unused segment outputs should be left open-circuit. 6.10 backplane outputs the lcd drive section includes four backplane outputs bp0 to bp3 which should be connected directly to the lcd. the backplane output signals are generated in accordance with the selected lcd drive mode. if less than four backplane outputs are required the unused outputs can be left open-circuit. in the 1 : 3 multiplex drive mode bp3 carries the same signal as bp1, therefore these two adjacent outputs can be connected together to give enhanced drive capabilities. in the 1 : 2 multiplex drive mode bp0 and bp2, bp1 and bp3 respectively carry the same signals and may also be paired to increase the drive capabilities. in the static drive mode the same signal is carried by all four backplane outputs and they can be connected in parallel for very high drive requirements. 6.11 display ram the display ram is a static 40 4-bit ram which stores lcd data. a logic 1 in the ram bit-map indicates the on state of the corresponding lcd segment; similarly, a logic 0 indicates the off state. there is a one-to-one correspondence between the ram addresses and the segment outputs, and between the individual bits of a ram word and the backplane outputs. the first ram column corresponds to the 40 segments operated with respect to backplane bp0 (see fig.10). in multiplexed lcd applications the segment data of the second, third and fourth column of the display ram are time-multiplexed with bp1, bp2 and bp3 respectively. when display data is transmitted to the pcf8576 the display bytes received are stored in the display ram in accordance with the selected lcd drive mode. to illustrate the filling order, an example of a 7-segment numeric display showing all drive modes is given in fig.11; the ram filling organization depicted applies equally to other lcd types. with reference to fig.11, in the static drive mode the eight transmitted data bits are placed in bit 0 of eight successive display ram addresses. in the 1 : 2 multiplex drive mode the eight transmitted data bits are placed in bits 0 and 1 of four successive display ram addresses. in the 1 : 3 multiplex drive mode these bits are placed in bits 0, 1 and 2 of three successive addresses, with bit 2 of the third address left unchanged. this last bit may, if necessary, be controlled by an additional transfer to this address but care should be taken to avoid overriding adjacent data because full bytes are always transmitted. in the 1 : 4 multiplex drive mode the eight transmitted data bits are placed in bits 0, 1, 2 and 3 of two successive display ram addresses. fig.10 display ram bit-map showing direct relationship between display ram addresses and segment outputs, and between bits in a ram word and backplane outputs. 0 0 1 2 3 1234 3536373839 display ram addresses (rows) / segment outputs (s) display ram bits (columns) / backplane outputs (bp) mbe525 2001 oct 02 16 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 6.12 data pointer the addressing mechanism for the display ram is realized using the data pointer. this allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display ram. the sequence commences with the initialization of the data pointer by the load data pointer command. following this, an arriving data byte is stored starting at the display ram address indicated by the data pointer thereby observing the filling order shown in fig.11. the data pointer is automatically incremented in accordance with the chosen lcd configuration. that is, after each byte is stored, the contents of the data pointer are incremented by eight (static drive mode), by four (1 : 2 multiplex drive mode) or by two (1 : 4 multiplex drive mode). 6.13 subaddress counter the storage of display data is conditioned by the contents of the subaddress counter. storage is allowed to take place only when the contents of the subaddress counter agree with the hardware subaddress applied to a0, a1 and a2. the subaddress counter value is defined by the device select command. if the contents of the subaddress counter and the hardware subaddress do not agree then data storage is inhibited but the data pointer is incremented as if data storage had taken place. the subaddress counter is also incremented when the data pointer overflows. the storage arrangements described lead to extremely efficient data loading in cascaded applications. when a series of display bytes are sent to the display ram, automatic wrap-over to the next pcf8576 occurs when the last ram address is exceeded. subaddressing across device boundaries is successful even if the change to the next device in the cascade occurs within a transmitted character (such as during the 14th display data byte transmitted in 1 : 3 multiplex mode). 6.14 output bank selector this selects one of the four bits per display ram address for transfer to the display latch. the actual bit chosen depends on the particular lcd drive mode in operation and on the instant in the multiplex sequence. in 1 : 4 multiplex, all ram addresses of bit 0 are the first to be selected, these are followed by the contents of bit 1, bit 2 and then bit 3. similarly in 1 : 3 multiplex, bits 0, 1 and 2 are selected sequentially. in 1 : 2 multiplex, bits 0 and 1 are selected and, in the static mode, bit 0 is selected. the pcf8576 includes a ram bank switching feature in the static and 1 : 2 multiplex drive modes. in the static drive mode, the bank select command may request the contents of bit 2 to be selected for display instead of bit 0 contents. in the 1 : 2 drive mode, the contents of bits 2 and 3 may be selected instead of bits 0 and 1. this gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is assembled. 6.15 input bank selector the input bank selector loads display data into the display ram in accordance with the selected lcd drive configuration. display data can be loaded in bit 2 in static drive mode or in bits 2 and 3 in 1 : 2 drive mode by using the bank select command. the input bank selector functions independent of the output bank selector. 2001 oct 02 17 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 6.16 blinker the display blinking capabilities of the pcf8576 are very versatile. the whole display can be blinked at frequencies selected by the blink command. the blinking frequencies are integer multiples of the clock frequency; the ratios between the clock and blinking frequencies depend on the mode in which the device is operating, as shown in table 3. an additional feature is for an arbitrary selection of lcd segments to be blinked. this applies to the static and 1 : 2 lcd drive modes and can be implemented without any communication overheads. by means of the output bank selector, the displayed ram banks are exchanged with alternate ram banks at the blinking frequency. this mode can also be specified by the blink command. in the 1 : 3 and 1 : 4 multiplex modes, where no alternate ram bank is available, groups of lcd segments can be blinked by selectively changing the display ram data at fixed time intervals. if the entire display is to be blinked at a frequency other than the nominal blinking frequency, this can be effectively performed by resetting and setting the display enable bit e at the required rate using the mode set command. table 3 blinking frequencies blinking mode normal operating mode ratio power-saving mode ratio nominal blinking frequency off -- blinking off 2hz 2hz 1hz 1hz 0.5 hz 0.5 hz f clk 92160 ---------------- f clk 15360 ---------------- f clk 184320 ------------------- - f clk 30720 ---------------- f clk 368640 ------------------- - f clk 61440 ---------------- this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 2001 oct 02 18 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 handbook, full pagewidth mbk389 s 2 n s 1 n s 7 n s n s n s 3 n s 5 n s 2 n s 3 n s 1 n s 1 n s 1 n s 2 n s n s 6 n s n s 4 n dp dp dp dp a f b g e c d a f b g e c d a f b g e c d a f b g e c d bp0 bp0 bp0 bp1 bp1 bp2 bp1 bp2 bp3 bp0 n c x x x 0 1 2 3 b x x x a x x x f x x x g x x x e x x x d x x x dp x x x n1 n2 n3 n4 n5 n6 n7 bit/ bp n a b x x 0 1 2 3 f g x x e c x x d dp x x n1 n2 n3 bit/ bp n b dp c x 0 1 2 3 a d g x f e x x n1 n2 bit/ bp n a c b dp 0 1 2 3 f e g d n1 bit/ bp cbaf geddp abf gecddp bdpcadgf e ac bdpf egd msb lsb msb lsb msb lsb msb lsb drive mode static 1 : 2 multiplex 1 : 3 multiplex 1 : 4 multiplex lcd segments lcd backplanes display ram filling order transmitted display byte x = data bit unchanged. fig.11 relationships between lcd layout, drive mode, display ram filling order and display data transmitted over the i 2 c-bus. 2001 oct 02 19 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 7 characteristics of the i 2 c-bus the i 2 c-bus is for bidirectional, two-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. 7.1 bit transfer (see fig.12) one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as a control signal. 7.2 start and stop conditions (see fig.13) both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line, while the clock is high is defined as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p). 7.3 system con?guration (see fig.14) a device generating a message is a transmitter, a device receiving a message is the receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves. 7.4 acknowledge (see fig.15) the number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlimited. each byte of eight bits is followed by an acknowledge bit. the acknowledge bit is a high level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges must pull-down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event the transmitter must leave the data line high to enable the master to generate a stop condition. 7.5 pcf8576 i 2 c-bus controller the pcf8576 acts as an i 2 c-bus slave receiver. it does not initiate i 2 c-bus transfers or transmit data to an i 2 c-bus master receiver. the only data output from the pcf8576 are the acknowledge signals of the selected devices. device selection depends on the i 2 c-bus slave address, on the transferred command data and on the hardware subaddress. in single device application, the hardware subaddress inputs a0, a1 and a2 are normally connected to v ss which defines the hardware subaddress 0. in multiple device applications a0, a1 and a2 are connected to v ss or v dd in accordance with a binary coding scheme such that no two devices with a common i 2 c-bus slave address have the same hardware subaddress. in the power-saving mode it is possible that the pcf8576 is not able to keep up with the highest transmission rates when large amounts of display data are transmitted. if this situation occurs, the pcf8576 forces the scl line to low until its internal operations are completed. this is known as the clock synchronization feature of the i 2 c-bus and serves to slow down fast transmitters. data loss does not occur. 7.6 input ?lters to enhance noise immunity in electrically adverse environments, rc low-pass filters are provided on the sda and scl lines. 7.7 i 2 c-bus protocol two i 2 c-bus slave addresses (0111000 and 0111001) are reserved for the pcf8576. the least significant bit of the slave address that a pcf8576 will respond to is defined by the level connected at its input pin sa0. therefore, two types of pcf8576 can be distinguished on the same i 2 c-bus which allows: up to 16 pcf8576s on the same i 2 c-bus for very large lcd applications the use of two types of lcd multiplex on the same i 2 c-bus. the i 2 c-bus protocol is shown in fig.16. the sequence is initiated with a start condition (s) from the i 2 c-bus master which is followed by one of the two pcf8576 slave addresses available. all pcf8576s with the corresponding sa0 level acknowledge in parallel with the slave address but all pcf8576s with the alternative sa0 level ignore the whole i 2 c-bus transfer. 2001 oct 02 20 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 after acknowledgement, one or more command bytes (m) follow which define the status of the addressed pcf8576s. the last command byte is tagged with a cleared most significant bit, the continuation bit c. the command bytes are also acknowledged by all addressed pcf8576s on the bus. after the last command byte, a series of display data bytes (n) may follow. these display bytes are stored in the display ram at the address specified by the data pointer and the subaddress counter. both data pointer and subaddress counter are automatically updated and the data is directed to the intended pcf8576 device. the acknowledgement after each byte is made only by the (a0, a1 and a2) addressed pcf8576. after the last display byte, the i 2 c-bus master issues a stop condition (p). 7.8 command decoder the command decoder identifies command bytes that arrive on the i 2 c-bus. all available commands carry a continuation bit c in their most significant bit position (fig.17). when this bit is set, it indicates that the next byte of the transfer to arrive will also represent a command. if this bit is reset, it indicates the last command byte of the transfer. further bytes will be regarded as display data. the five commands available to the pcf8576 are defined in table 4. fig.12 bit transfer. mba607 data line stable; data valid change of data allowed sda scl fig.13 definition of start and stop conditions. handbook, full pagewidth mbc622 sda scl p stop condition sda scl s start condition 2001 oct 02 21 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 fig.14 system configuration. mga807 sda scl master transmitter/ receiver master transmitter slave transmitter/ receiver slave receiver master transmitter/ receiver fig.15 acknowledgement on the i 2 c-bus. handbook, full pagewidth mbc602 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master 2001 oct 02 22 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 fig.16 i 2 c-bus protocol. handbook, full pagewidth mbk279 s a 0 s 011100 0ac command a p a display data slave address / rw acknowledge by all addressed pcf8576s acknowledge by a0, a1 and a2 selected pcf8576 only n 0 byte(s) n 1 byte(s) 1 byte update data pointers and if necessary, subaddress counter fig.17 general format of command byte. c = 0; last command. c = 1; commands continue. msa833 rest of opcode c msb lsb 2001 oct 02 23 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 table 4 de?nition of pcf8576 commands command opcode options description mode set c 1 0 lp e b m1 m0 table 5 de?nes lcd drive mode. table 6 de?nes lcd bias con?guration. table 7 de?nes display status. the possibility to disable the display allows implementation of blinking under external control. table 8 de?nes power dissipation mode. load data pointer c 0 p5 p4 p3 p2 p1 p0 table 9 six bits of immediate data, bits p5 to p0, are transferred to the data pointer to de?ne one of forty display ram addresses. device select c 1 1 0 0 a2 a1 a0 table 10 three bits of immediate data, bits a2 to a0, are transferred to the subaddress counter to de?ne one of eight hardware subaddresses. bank select c11110 i o table11 de?nes input bank selection (storage of arriving display data). table 12 de?nes output bank selection (retrieval of lcd display data). the bank select command has no effect in 1 : 3 and 1 : 4 multiplex drive modes. blink c 1 1 1 0 a bf1 bf0 table 13 de?nes the blinking frequency. table 14 selects the blinking mode; normal operation with frequency set by bf1, bf0 or blinking by alternation of display ram banks. alternation blinking does not apply in 1 : 3 and 1 : 4 multiplex drive modes. table 5 mode set option 1 table 6 mode set option 2 table 7 mode set option 3 table 8 mode set option 4 table 9 load data pointer option 1 table 10 device select option 1 table 11 bank select option 1 lcd drive mode bits drive mode backplane m1 m0 static 1 bp 0 1 1 : 2 mux (2 bp) 1 0 1 : 3 mux (3 bp) 1 1 1 : 4 mux (4 bp) 0 0 lcd bias bit b 1 3 bias 0 1 2 bias 1 display status bit e disabled (blank) 0 enabled 1 mode bit lp normal mode 0 power-saving mode 1 description bits 6-bit binary value of 0 to 39 p5 p4 p3 p2 p1 p0 description bits 3-bit binary value of 0 to 7 a2 a1 a0 static 1 : 2 mux bit i ram bit 0 ram bits 0 and 1 0 ram bit 2 ram bits 2 and 3 1 2001 oct 02 24 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 table 12 bank select option 2 table 13 blink option 1 table 14 blink option 2 7.9 display controller the display controller executes the commands identified by the command decoder. it contains the status registers of the pcf8576 and co-ordinates their effects. the controller is also responsible for loading display data into the display ram as required by the filling order. static 1 : 2 mux bit o ram bit 0 ram bits 0 and 1 0 ram bit 2 ram bits 2 and 3 1 blink frequency bits bf1 bf0 off 0 0 2hz 0 1 1hz 1 0 0.5 hz 1 1 blink mode bit a normal blinking 0 alternation blinking 1 7.10 cascaded operation in large display configurations, up to 16 pcf8576s can be distinguished on the same i 2 c-bus by using the 3-bit hardware subaddress (a0, a1 and a2) and the programmable i 2 c-bus slave address (sa0). when cascaded pcf8576s are synchronized so that they can share the backplane signals from one of the devices in the cascade. such an arrangement is cost-effective in large lcd applications since the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display. the other pcf8576s of the cascade contribute additional segment outputs but their backplane outputs are left open-circuit (see fig.18). the sync line is provided to maintain the correct synchronization between all cascaded pcf8576s. this synchronization is guaranteed after the power-on reset. the only time that sync is likely to be needed is if synchronization is accidentally lost (e.g. by noise in adverse electrical environments; or by the definition of a multiplex mode when pcf8576s with differing sa0 levels are cascaded). sync is organized as an input/output pin; the output selection being realized as an open-drain driver with an internal pull-up resistor. a pcf8576 asserts the sync line at the onset of its last active backplane signal and monitors the sync line at all other times. should synchronization in the cascade be lost, it will be restored by the first pcf8576 to assert sync. the timing relationship between the backplane waveforms and the sync signal for the various drive modes of the pcf8576 are shown in fig.19. for single plane wiring of packaged pcf8576s and chip-on-glass cascading, see chapter 12. 2001 oct 02 25 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 fig.18 cascaded pcf8576 configuration. handbook, full pagewidth host micro- processor/ micro- controller sda scl clk osc sync 1 17 to 56 2 3 4 6 78 512 91011 7 8 9 10 11 40 segment drives 4 backplanes 40 segment drives lcd panel (up to 2560 elements) pcf8576 a0 a1 a2 ss sa0 v ss v dd v lcd v dd v lcd v mbk280 sda scl sync clk osc 1 512 2 3 4 6 17 to 56 13, 15 14, 16 13, 15 14, 16 bp0 to bp3 (open-circuit) a0 a1 a2 sa0 v ss v dd v lcd pcf8576 bp0 to bp3 r t r 2c b 2001 oct 02 26 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 fig.19 synchronization of the cascade for the various pcf8576 drive modes. excessive capacitive coupling between scl or clk and sync may cause erroneous synchronization. if this proves to be a problem, the capacitance of the sync line should be increased (e.g. by an external capacitor between sync and v dd ). degradation of the positive edge of the sync pulse may be countered by an external pull-up resistor. handbook, full pagewidth t= frame f frame 1 bp0 sync bp1 (1/2 bias) sync bp2 (a) static drive mode. (b) 1 : 2 multiplex drive mode. (c) 1 : 3 multiplex drive mode. (d) 1 : 4 multiplex drive mode. bp3 sync sync bp1 (1/3 bias) mbe535 2001 oct 02 27 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 8 limiting values in accordance with the absolute maximum rating system (iec 60134). 9 handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling mos devices (see handling mos devices ). symbol parameter min. max. unit v dd supply voltage - 0.5 +11.0 v v lcd lcd supply voltage v dd - 11.0 v dd v v i input voltage sda, scl, clk, sync, sa0, osc, a0 to a2 v ss - 0.5 v dd + 0.5 v v o output voltage s0 to s39, bp0 to bp3 v lcd - 0.5 v dd + 0.5 v i i dc input current - 20 ma i o dc output current - 25 ma i dd , i ss , i lcd v dd , v ss or v lcd current - 50 ma p tot total power dissipation - 400 mw p o power dissipation per output - 100 mw t stg storage temperature - 65 +150 c 2001 oct 02 28 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 10 dc characteristics v dd = 2 to 9 v; v ss =0v; v lcd =v dd - 2vtov dd - 9 v; t amb = - 40 to +85 c; unless otherwise speci?ed. notes 1. v lcd v dd - 3 v for 1 3 bias. 2. lcd outputs are open-circuit; inputs at v ss or v dd ; external clock with 50% duty factor; i 2 c-bus inactive. 3. resets all logic when v dd 2001 oct 02 30 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 fig.21 driver timing waveforms. handbook, full pagewidth mbe545 0.7v dd 0.3v dd 1/ f clk t psync t clkh t clkl 0.7v dd 0.3v dd sync clk 0.5 v 0.5 v t plcd bp0 to bp3, and s0 to s39 t psync t syncl (v dd = 5 v) fig.22 i 2 c-bus timing waveforms. handbook, full pagewidth sda mga728 sda scl t su;sta t su;sto t hd;sta t buf t low t hd;dat t high t r t f t su;dat 2001 oct 02 31 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 11.1 typical supply current characteristics fig.23 - i ss as a function of f frame . v dd = 5 v; v lcd = 0 v; t amb =25 c. 0 200 50 0 10 mbe530 20 30 40 100 i ss ( m a ) f (hz) frame normal mode power-saving mode fig.24 - i lcd as a function of f frame . v dd = 5 v; v lcd = 0 v; t amb =25 c. 0 200 50 0 10 mbe529 20 30 40 100 i lcd ( m a ) f (hz) frame fig.25 i ss as a function of v dd . v lcd = 0 v; external clock; t amb =25 c. handbook, halfpage 010 50 0 10 mbe528 - 1 20 30 40 5 i ss ( m a ) v (v) dd power-saving mode f = 35 khz clk normal mode f = 200 khz clk fig.26 i lcd as a function of v dd . v lcd = 0 v; external clock; f clk = nominal frequency. handbook, halfpage 010 50 0 10 mbe527 - 1 20 30 40 5 v (v) dd i lcd ( m a ) 85 c o 25 c o 40 c o 2001 oct 02 32 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 11.2 typical characteristics of lcd outputs fig.27 r o(max) as a function of v dd . v lcd = 0 v; t amb =25 c. handbook, halfpage 6 0 10 -1 mbe532 - 1 1 10 3 v (v) dd r s r bp r o(max) (k w) fig.28 r o(max) as a function of t amb . v dd = 5 v; v lcd =0v. 40 0 40 120 2.5 0 2.0 mbe526 80 1.5 1.0 0.5 r s r bp r o(max) (k w) t amb ( c) o 2001 oct 02 33 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 12 application information a ndbook, full pagewidth pcf8576t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 sda scl sync clk v osc a0 a1 a2 sa0 v v bp0 bp2 bp1 bp3 s0 s1 s2 s3 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 s39 s38 s37 s36 s35 s34 s33 s32 s31 s30 s29 s28 s27 s26 s25 s24 s23 s22 s21 34 33 s17 s7 s8 s9 s10 s11 32 31 30 29 s16 s15 s13 s14 s12 dd ss lcd pcf8576t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 bp0 bp2 bp1 bp3 s40 s41 s42 s43 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 s79 s78 s77 s76 s75 s74 s73 s72 s71 s70 s69 s68 s67 s66 s65 s64 s63 s62 s61 34 33 s57 s47 s48 s49 s50 s51 s51 s52 s53 32 31 30 29 s56 s55 s53 s54 s52 s50 s39 s40 s13 s12 open s10 s11 s0 s79 backplanes segments mbk281 sda scl sync clk v v v dd ss lcd fig.29 single plane wiring of packaged pcf8576ts. 2001 oct 02 34 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 12.1 chip-on-glass cascadability in single plane in chip-on-glass technology, where driver devices are bonded directly onto glass of the lcd, it is important that the devices may be cascaded without the crossing of conductors, but the paths of conductors can be continued on the glass under the chip. all of this is facilitated by the pcf8576 bonding pad layout (see fig.30). pads needing bus interconnection between all pcf8576s of the cascade are v dd , v ss , v lcd , clk, scl, sda and sync. these lines may be led to the corresponding pads of the next pcf8576 through the wide opening between v lcd pad and the backplane output pads. the only bus line that does not require a second opening to lead through to the next pcf8576 is v lcd , being the cascade centre. the placing of v lcd adjacent to v ss allows the two supplies to be connected together. when an external clocking source is to be used, osc of all devices should be connected to v dd . the pads osc, a0, a1, a2 and sa0 have been placed between v ss and v dd to facilitate wiring of oscillator, hardware subaddress and slave address. 13 bonding pad information fig.30 bonding pad locations. bonding pad dimensions: 120 120 m m. gold bump dimensions: 94 94 25 m m. handbook, full pagewidth mbk282 1 2 3 4 5 6 7 8 9 10 11 12 13 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 s17 s16 s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 bp3 bp1 bp2 bp0 v lcd v ss sa0 a2 a1 a0 osc v dd clk scl sda s39 s38 s37 s36 s35 s34 s33 s32 s31 s30 s29 s28 s27 s26 s25 s24 s23 s22 s21 s20 s19 s18 sync 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 14 pcf8576 x y 0 0 cascade centre 3.07 mm 4.12 mm 2001 oct 02 35 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 table 15 bonding pad locations (dimensions in m m) all x and y coordinates are referenced to centre of chip (see fig.30). table 16 bonding pad dimensions symbol pad coordinates xy sda 1 - 155 - 1900 scl 2 45 - 1900 sync 3 245 - 1900 clk 4 445 - 1900 v dd 5 645 - 1900 osc 6 865 - 1900 a0 7 1105 - 1900 a1 8 1375 - 1900 a2 9 1375 - 1700 sa0 10 1375 - 1500 v ss 11 1375 - 1300 v lcd 12 1375 - 1100 bp0 13 1375 300 bp2 14 1375 500 bp1 15 1375 700 bp3 16 1375 900 s0 17 1375 1100 s1 18 1375 1300 s2 19 1375 1500 s3 20 1375 1700 s4 21 1375 1900 s5 22 1105 1900 s6 23 865 1900 s7 24 645 1900 s8 25 445 1900 s9 26 245 1900 s10 27 45 1900 s11 28 - 155 1900 s12 29 - 355 1900 s13 30 - 555 1900 s14 31 - 755 1900 s15 32 - 955 1900 s16 33 - 1155 1900 s17 34 - 1375 1900 s18 35 - 1375 1660 s19 36 - 1375 1420 s20 37 - 1375 1200 s21 38 - 1375 1000 s22 39 - 1375 800 s23 40 - 1375 600 s24 41 - 1375 400 s25 42 - 1375 200 s26 43 - 1375 - 200 s27 44 - 1375 - 400 s28 45 - 1375 - 600 s29 46 - 1375 - 800 s30 47 - 1375 - 1000 s31 48 - 1375 - 1200 s32 49 - 1375 - 1420 s33 50 - 1375 - 1660 s34 51 - 1375 - 1900 s35 52 - 1155 - 1900 s36 53 - 955 - 1900 s37 54 - 755 - 1900 s38 55 - 555 - 1900 s39 56 - 355 - 900 pad pitch 200 m m pad size, aluminium 120 120 m m gold bump dimensions 94 94 25 m m symbol pad coordinates xy 2001 oct 02 36 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 14 tray information: PCF8576U handbook, full pagewidth x y f h mgu431 d e a g 1,1 x,1 2,1 1,2 1,y x,y c b m j a a section a-a fig.31 tray details. for dimensions see table 18. table 17 tray dimensions (see fig.33) handbook, halfpage mgu432 pc8576u fig.32 tray alignment. the orientation of the ic in a pocket is indicated by the position of the ic type name on the die surface with respect to the chamfer on the upper left corner of the tray. symbol description value a pocket pitch; x direction 6.32 mm b pocket pitch; y direction 6.32 mm c pocket width; x direction 4.55 mm d pocket width; y direction 4.55 mm e tray width; x direction 50.67 mm f tray width; y direction 50.67 mm g cut corner to pocket 1,1 centre 6.32 mm h cut corner to pocket 1,1 centre 6.32 mm j tray thickness 3.94 mm m pocket depth 0.61 mm x number of pockets; x direction 7 y number of pockets; y direction 7 2001 oct 02 37 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 15 tray information: PCF8576U/2 handbook, full pagewidth 1,1 x,1 2,1 1,2 1,y x,y x y f h g d a c b mgw014 e k l m j a a section a-a fig.33 tray details. for dimensions see table 17. table 18 tray dimensions (see fig.31) handbook, halfpage mgw015 PCF8576U/2 fig.34 tray alignment. the orientation of the ic in a pocket is indicated by the position of the ic type name on the die surface with respect to the chamfer on the upper left corner of the tray. symbol description value a pocket pitch; x direction 5.33 mm b pocket pitch; y direction 7.11 mm c pocket width; x direction 3.43 mm d pocket width; y direction 4.67 mm e tray width; x direction 50.67 mm f tray width; y direction 50.67 mm g cut corner to pocket 1,1 centre 6.67 mm h cut corner to pocket 1,1 centre 7.56 mm j tray thickness 3.94 mm k tray cross section 1.76 mm l tray cross section 2.46 mm m pocket depth 0.89 mm x number of pockets; x direction 8 y number of pockets; y direction 6 2001 oct 02 38 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 16 package outlines unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm inches 0.3 0.1 3.0 2.8 0.25 0.42 0.30 0.22 0.14 21.65 21.35 11.1 11.0 0.75 15.8 15.2 1.45 1.30 0.90 0.55 7 0 o o 0.1 0.1 dimensions (inch dimensions are derived from the original mm dimensions) 1.6 1.4 sot190-1 96-04-02 97-08-11 w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a x (a ) 3 a y 56 29 28 1 pin 1 index 0.012 0.004 0.12 0.11 0.017 0.012 0.0087 0.0055 0.85 0.84 0.44 0.43 0.0295 2.25 0.089 0.62 0.60 0.057 0.051 0.035 0.022 0.004 0.2 0.008 0.004 0.063 0.055 0.01 0 5 10 mm scale vso56: plastic very small outline package; 56 leads sot190-1 a max. 3.3 0.13 note 1. plastic or metal protrusions of 0.3 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 2001 oct 02 39 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 17 soldering 17.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. 17.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 220 c for thick/large packages, and below 235 c for small/thin packages. 17.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 17.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 2001 oct 02 40 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 17.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package soldering method wave reflow (1) bga, hbga, lfbga, sqfp, tfbga not suitable suitable hbcc, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable 2001 oct 02 41 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 18 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. data sheet status (1) product status (2) definitions objective speci?cation development this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. preliminary speci?cation quali?cation this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. product speci?cation production this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. changes will be communicated according to the customer product/process change noti?cation (cpcn) procedure snw-sq-650a. 19 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 20 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. bare die ? all die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of philips' delivery. if there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. there are no post packing tests performed on individual die or wafer. philips semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. accordingly, philips semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. it is the responsibility of the customer to test and qualify their application in which the die is used. 2001 oct 02 42 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 21 purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011. 2001 oct 02 43 philips semiconductors product speci?cation universal lcd driver for low multiplex rates pcf8576 notes ? koninklijke philips electronics n.v. 2001 sca73 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands 403512/04/pp 44 date of release: 2001 oct 02 document order number: 9397 750 08044 |
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